ASIC Design Engineer - Hardware

The Inria Center at the University of Rennes is one of Inria’s eight research centers and is home to more than thirty research teams. The center is a major and internationally recognized player in the field of digital sciences. It is at the heart of a rich R&D and innovation ecosystem, bringing together highly innovative SMEs, large industrial groups, competitiveness clusters, research and higher education institutions, laboratories of excellence, and a technological research institute.

The TARAN team at Inria and the University of Rennes is looking for passionate and motivated Digital Design Engineers seeking to make an impact in the fields of computer architecture and AI hardware accelerators. The right candidate will not be afraid to attack complex problems and assume broad ownership, ranging from chip or block architecture, programming models, through RTL implementation, design verification, physical design, and DFT.

Are you an experienced or young engineer interested in ASIC design and looking for an exciting opportunity to advance your career? Join our team, where we design and verify hardware prototypes of processors and AI accelerators to support our research. We are seeking a creative and skilled colleague to help develop chips (ASICs) or FPGA prototypes. Are you looking for broader exposure across multiple IP designs? Do you want the opportunity to work globally within a recognized research team to deliver innovative systems? Join us to help shape the future of our research!

As a hardware design engineer, you will design solutions for different hardware prototypes. Your goal will be to achieve maximum efficiency in power consumption, performance, and area while ensuring correct functional behavior. Your key responsibilities will include participating in the whole design flow:
- Participating in creating plans and defining the microarchitecture.
- Developing system-level RTL code using System Verilog or VHDL.
- Running design checks and identifying and fixing bugs.
- Physical design (placement and routing) of the chip using the latest industrial methodologies and tools.
- Back-end design and verification.

The host team has access to tools from major EDA companies (Synopsys, Siemens EDA, Cadence) and to advanced ASIC technology PDKs (22nm, 16nm, 7nm).

Collaboration with researchers and engineers across the architecture, verification, performance analysis, power analysis, implementation, and various IP functions is essential to achieve success in our projects.

The position is funded by a large project, CAMELIA, involving several academic partners from France. The CAMELIA (Hardware and Software Components for Advanced AI Accelerators) program focuses on developing scalable, modular AI acceleration components and their associated software environment. It aims to create specialized accelerators based on chiplets and 2.5D/3D integration that target key functions for executing AI models, using a joint hardware/software/application co-design approach. Anticipating breakthroughs in both hardware and software, the program aims to achieve significant performance gains—particularly in energy efficiency—compared to current industry solutions based on GPUs or NPUs.

More specifically, it targets the design of chiplets dedicated to accelerating key functions (tensor computation, sparse computation, dynamic low-precision management), their integration into modular systems-on-chip, and the optimization of the associated software stack for compilation, orchestration, and application development. As the project matures, it will also incorporate constraints related to cost, safety, security, and environmental responsibility.

Inside CAMELIA, the position is focused on the design and verification (RTL, Physical) of the AI accelerator, similar in spirit to Google's TPU, but with specific features proposed by some of the academic partners.

The position is for a one-year term, but it may be extended for up to 6 years, which is the duration of the CAMELIA project.

Required Skills And Experience

- You graduated from a University or Engineering School, in Computer Science, Computer Engineering or Electronic / Electrical Engineering
- Solid understanding of SoC / ASIC design methodologies and techniques with hands-on experience of SoC design and integration for complex SoC
- Experience in RTL design using Verilog, System Verilog or VHDL
- Experience or knowledge in back-end design methodologies and tools (place and route) is a plus.
- Knowledge of at least one full ASIC implementation flow.

“Nice To Have” Skills And Experience

- Have knowledge of AMBA protocol like AXI/AHB/APB/CHI
- Understanding of memory controller, microprocessors, and debug architecture
- Knowledge of basic scripting languages, e.g., Perl/TCL/Python
- Experience with Linux, shell scripts, Makefiles, and repository management systems like GIT
- Knowledge of hardware verification techniques
- Familiar with embedded C, assembly, and compilers

• Subsidized meals
• Partial reimbursement of public transport costs
• Leave: 7 weeks of annual leave + 10 extra days off due to RTT (statutory reduction in working hours) + possibility of exceptional leave (sick children, moving home, etc.)
• Possibility of teleworking (after 6 months of employment) and flexible organization of working hours
• Professional equipment available (videoconferencing, loan of computer equipment, etc.)
• Social, cultural and sports events and activities
• Access to vocational training

monthly gross salary from 2695 euros according to diploma and experience