PhD Position F/M Architectural study of hardware AI accelerators distributed on chiplets

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Contract type : Fixed-term contract

Level of qualifications required : Graduate degree or equivalent

Fonction : PhD Position

Level of experience : Recently graduated

About the research centre or Inria department

The Centre Inria de l’Université de Grenoble groups together almost 450 people in 26 research teams and 9 research support departments.

Staff is present on three campuses in Grenoble, in close collaboration with other research and higher education institutions (Université Grenoble Alpes, CNRS, CEA, INRAE, …), but also with key economic players in the area.

The Centre Inria de l’Université Grenoble Alpes is active in the fields of high-performance computing, verification and embedded systems, modeling of the environment at multiple levels, and data science and artificial intelligence. The center is a top-level scientific institute with an extensive network of international collaborations in Europe and the rest of the world.

Context

As part of the CAMELIA project (national AI strategy), the MADMAX team is looking to recruit a PhD student in hardware architecture for the design of digital circuits accelerating AI workloads.

The objective is to study the design of hardware accelerators physically distributed over chiplets, focusing on partitioning, scheduling, optimization, and hardware implementation issues.

Assignment

      Missions :
  • Research, development of prototypes and demonstrators, publication of results
   To gain a better understanding of the proposed research topic :
  • 2020-06 – Ultra Low-latency, Low-area Inference Accelerators using Heterogeneous Deep Quantization with QKeras and hls4ml
  • 2021-05 FCCM – unzipFPGA: Enhancing FPGA-based CNN Engines with On-the-Fly Weights Generation
  • 2020-11 ICFPT – Memory-Efficient Dataflow Inference for Deep CNNs on FPGA
  • 2024-08 – H2PIPE High Throughput CNN Inference on FPGAs with High-Bandwidth Memory
  • 2023-03 – FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA
   Collaboration:
  • The PhD thesis will take place within the context of a national project, involving collaborations with all project members.

Main activities

Main activities :
 
- Literature review, conducted throughout the 3-year PhD
- Exploration of theoretical and practical solutions
- Implementation and evaluation of solutions
- Drafting of research publications

Skills

Technical skills and level required :

- Expert level in RTL design, FPGA and architecture at large

- Languages : English, French is a plus

 

Benefits package

  • Subsidized meals
  • Partial reimbursement of public transport costs
  • Leave: 7 weeks of annual leave + 10 extra days off due to RTT (statutory reduction in working hours) + possibility of exceptional leave (sick children, moving home, etc.)
  • Possibility of teleworking (after 6 months of employment) and flexible organization of working hours
  • Professional equipment available (videoconferencing, loan of computer equipment, etc.)
  • Social, cultural and sports events and activities
  • Access to vocational training
  • Social security coverage under conditions

Remuneration

2300 euros gross salary /month