2018-01027 - Scheduling, mapping and code generation of partially expanded dataflow graphs

Type de contrat : CDD de la fonction publique

Contrat renouvelable : Oui

Niveau de diplôme exigé : Thèse ou équivalent

Fonction : Post-Doctorant

A propos du centre ou de la direction fonctionnelle

The Inria Rennes - Bretagne Atlantique Centre is one of Inria's eight centres and has more than thirty research teams. The Inria Center is a major and recognized player in the field of digital sciences. It is at the heart of a rich R&D and innovation ecosystem: highly innovative PMEs, large industrial groups, competitiveness clusters, research and higher education players, laboratories of excellence, technological research institute, etc.

Contexte et atouts du poste

The goal of this post-doctorate is to participate in a project to develop a scheduler synthesis toolsuite that exploits partial expansion graphs (PEG) and affine dataflow graphs (ADFG) to generate efficient schedules of real-time parallel applications on many-core architectures.  Starting from the initial implementation of an application modeled as a synchronous data flow graph with parameterized actors, we will investigate implementations using parameterized graphs and/or code generation techniques.

The ADFG tool will then be used to compute the scheduling and mapping of the implemented application.  Scheduling and mapping will require us to investigate open problems such as shared memory access contentions and optimal FIFO channel allocations. The scheduler will be either time-triggered or deferred to the application implementation (ASAP, RM or DM). A timing analysis case study will additionally be performed by a profiling tool (e.g., valgrind) and/or the WCET analysis tool Heptane of the Inria PACAP team.

Mission confiée

Candidates must have a strong and demonstrated background in scheduling analysis and RTES design, synchronous, cyclo-static dataflow and Kahn process networks, WCET analysis and profiling as well as C and Java programming. Knowledge and experience of PEG and familiarity with the ADFG tool and the DSPCAD framework (DIF-GPU, DICE and LIDE) will be pluses.­

The successful applicant will join Inria project-team TEA (with benefits according to Inria salary and social benefits standards) and participate to an ongoing project in collaboration with the University of Maryland.  The initial appointment will be of ten month and possibly renewed in the context of an upcoming Insa-IETR-Inria Chair.

Principales activités

The goal of this post-doctorate is to participate in a project to develop a scheduler synthesis toolsuite that exploits partial expansion graphs (PEG) and affine dataflow graphs (ADFG) to generate efficient schedules of real-time parallel applications on many-core architectures.  Starting from the initial implementation of an application modeled as a synchronous data flow graph with parameterized actors, we will investigate implementations using parameterized graphs and/or code generation techniques.

Avantages sociaux

  • Subsidised catering service
  • Partially-reimbursed public transport

Rémunération

monthly gross salary amounting to 2653 euros