Post-Doctoral Research Visit F/M Reliability & Security of Modern Hardware Accelerators Based on Conventional and Emerging Technologies

The Inria Centre at Rennes University is one of Inria's eight centres and has more than thirty research teams. The Inria Centre is a major and recognized player in the field of digital sciences. It is at the heart of a rich R&D and innovation ecosystem: highly innovative PMEs, large industrial groups, competitiveness clusters, research and higher education players, laboratories of excellence, technological research institute, etc.

The TARAN research group at INRIA/IRISA (Rennes, France) is accepting applications for a postdoctoral researcher in the area of reliability and security of modern hardware accelerators based on both conventional and emerging in memory technologies for safety- and mission-critical computing. The position is funded through ongoing European and National research projects in collaboration with academic and industrial partners.

Context and Motivation

The deployment of specialized hardware accelerators has become a cornerstone of modern computing platforms. Devices ranging from graphics and tensor processing units (GPUs and TPUs) to emerging processing-in-memory (PIM) architectures are now used to efficiently execute increasingly data-intensive workloads, particularly for large-scale AI models whose parameters reach billions to trillions. Unlike traditional CPU-centric designs, modern accelerators provide massively parallel compute capabilities and reduce data movement overheads, enabling onboard processing for domains such as autonomous robotics, remote sensing, and complex signal processing.

This trend is particularly visible in safety- and mission-critical domains. Small satellites increasingly integrate COTS SoCs with AI accelerators for on-board inference and radar processing, while automotive, avionics, and medical systems rely on accelerators for perception, decision-making, and classification. In these contexts, strict correctness and timing constraints, combined with harsh conditions such as radiation, voltage and temperature variations, and long operational lifetimes, impose strong reliability and security requirements on compute-dense accelerators.

As these workloads become both memory-bound and specialized accelerator-dominated, evaluating how faults propagate through the hardware and into algorithmic layers, potentially corrupting neural network outputs, control decisions, or mission-critical computations, has become a central research challenge. Understanding these failure modes is essential not only for safety but also for security, as similar fault mechanisms can be exploited to launch fault attacks or cause integrity violations in accelerator-based computing systems. 

In this context, this postdoctoral position is centered on driving decisive advances in the reliability and security of modern hardware accelerators, with the expectation of producing robust, high-impact results that shape both research and practice in safety-critical computing systems. The postdoctoral researcher will work closely with the team and benefit from strong guidance. The candidate is expected to contribute to the conception and writing of innovative, forward-looking research projects, offering a valuable opportunity to help shape the field's research agenda.

Recent research directions within the team focus on reliability analysis and fault protection for Artificial Intelligence (AI) inference. Specifically, we investigate radiation experiments [1,3,4], cross-layer approaches [1,10], strategies for minimizing fault-injection time [8,9], and selective protection methods [1,5,8]. Additionally, we are exploring the relationship between approximate computing and reliability [6,7,11,12,13].

The postdoctoral researcher will be encouraged to take an active role in one or more of these research directions, advancing them while building a unifying research line that connects them.

Team reference publications

[1] “Cross-Layer Reliability Evaluation and Efficient Hardening of Large Vision Transformers Models”, Lucas Roquet, Fernando Fernandes dos Santos, Paolo Rech, Marcello Traiola, Olivier Sentieys, Angeliki Kritikakou, Design Automation Conference (DAC), 2024

[2] “Improving Deep Neural Network Reliability via Transient-Fault-Aware Design and Training”, Fernando Fernandes dos Santos, Niccolò Cavagnero, Marco Ciccone, Giuseppe Averta, Angeliki Kritikakou, Olivier Sentieys, Paolo Rech, Tatiana Tommasi, IEEE Transactions on Emerging Topics in Computing, 2024

[3] “Impact of Radiation-Induced Effects on Embedded GPUs Executing Large Machine Learning Models”, Bruno Loureiro Coelho, Fernando Fernandes dos Santos, Matteo Saveriano, Gregory Allen, Andrew Daniel, Steven Guertin, Sergeh Vartania, Edward Wyrwas, Christopher Frost, Paolo Rech, IEEE Transactions on Nuclear Science, 2025

[4] “Impact of High-Level-Synthesis on Reliability of Artificial Neural Network Hardware Accelerators”, Marcello Traiola, Fernando Fernandes dos Santos, Paolo Rech, Carlo Cazzaniga, Olivier Sentieys, Angeliki Kritikakou, IEEE Transactions on Nuclear Science, 2024,

[5] “HTAG-eNN: Hardening Technique with AND Gates for Embedded Neural Networks”, Wilfread Guilleme, Angeliki Kritikakou, Youri Helen, Cédric Killian, Daniel Chillet, Design Automation Conference (DAC), Jun 2024

[6] “SERA-Float: A Soft Error Resilient Approximate Floating-Point Computing Format”, Vishesh Mishra, Marcello Traiola, Angeliki Kritikakou, Olivier Sentieys, Urbi Chatterjee, International Conference On Computer Aided Design (ICCAD), 2025

[7] “A genetic approach for automatic AxC design exploration at RTL based on assertion mining and fault analysis”, Alberto Bosio, Samuele Germiniani, Graziano Pravadelli, Marcello Traiola, IEEE Transactions on Emerging Topics in Computing, 2025

[8] "harDNNing: a machine-learning-based framework for fault tolerance assessment and protection of DNNs," M. Traiola, A. Kritikakou and O. Sentieys, ETS 2023 

[9] "A machine-learning-guided framework for fault-tolerant DNNs," M. Traiola, A. Kritikakou and O. Sentieys, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023

[10] “FLODAM: Cross-Layer Reliability Analysis Flow for Complex Hardware Designs” Angeliki Kritikakou, Olivier Sentieys, Guillaume Hubert, Youri Helen, Jean-Francois Coulon, Patrice Deroux-Dauphin, Design, Automation and Test in Europe (DATE), 2022

[11] “QAMR: an Approximation-Based Fully Reliable TMR Alternative for Area Overhead Reduction”, Bastien Deveautour, Marcello Traiola, Arnaud Virazel, and Patrick Girard, European Test Symposium (ETS), 2020

[12] “Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits”, Marcello Traiola, Jorge Echavarria, Alberto Bosio, Jürgen Teich, and Ian O'Connor, International Conference On Computer Aided Design (ICCAD). 2021

[13] “Approximate Fault-Tolerant Neural Network Systems”, Marcello Traiola, Salvatore Pappalardo, Ali Piri, Annachiara Ruospo, Bastien Deveautour, Ernesto Sanchez, Alberto Bosio, Sepide Saeedi, Alessio Carpegna, Anıl Bayram Göğebakan, Enrico Magliano, and Alessandro Savino, European Test Symposium (ETS), 2024

Other publications from TARAN: https://team.inria.fr/taran/publications/

Research Scope

The postdoc will contribute to the development of models, methodologies, and tools to understand and improve the reliability and security of accelerator-based computing platforms. Possible directions include (but are not limited to):

• evaluation of transient, permanent, and aging-related faults in accelerators
• cross-layer analysis of fault propagation from hardware to algorithm
• hardening strategies at the architecture and algorithm levels
• secure-by-design accelerator architectures (e.g., isolation, memory protection)
• interactions between fault tolerance and security
• defenses against fault attacks, malicious perturbations, or integrity violations
• reliability evaluation for emerging accelerators (e.g., TPUs, PIM, nonvolatile memories, RISC-V)
• modeling of failure modes under radiation, voltage/temperature stress, or long-duration operation

Both theoretical and experimental contributions are welcome, depending on the candidate's expertise.

Role and Responsibilities

This is a research-focused academic position, not an engineering or support role. Expected duties include:

• conducting original research and publishing in leading venues
• supervising and mentoring PhD students and Master’s interns
• participating in European and National research projects, including:
• research contributions in collaborative work packages
• project reporting and deliverables
• contribution to project design and writing for future calls
• interaction with industrial and academic partners
• presenting results at international conferences and consortium meetings

The position offers opportunities to work with simulation frameworks, accelerator testbeds, and radiation-testing facilities, depending on the research direction.

Candidate Profile

We are seeking applicants with a strong research background in at least one of the following areas:

• computer architecture
• hardware reliability or fault tolerance
• Hardware security or trusted computing
• hardware/software co-design
• microarchitecture simulation or fault modeling
• AI accelerator or PIM architecture design

Experience with publication, scientific communication, and student supervision is considered a strong asset.

Environment and Funding

• Institution: INRIA/IRISA (TARAN team), Rennes, France
• Funding: position funded through ongoing European and national research projects. Travel expenses are also covered.
• Collaboration: international academic and industrial partners
• Duration: 12–24 months (flexible depending on funding framework)
• Start date: 2026 (flexible)
• Salary: Monthly gross salary amounting to 2788 euros

Application Procedure

Applications should include:

1. Curriculum vitae with publication list
2. Contact information for at least two references

Review of applications will continue until the position is filled

• Subsidized meals
• Partial reimbursement of public transport costs
• Leave: 7 weeks of annual leave + 10 extra days off due to RTT (statutory reduction in working hours) + possibility of exceptional leave (sick children, moving home, etc.)
• Possibility of teleworking (after 6 months of employment) and flexible organization of working hours
• Professional equipment available (videoconferencing, loan of computer equipment, etc.)
• Social, cultural and sports events and activities
• Access to vocational training

Monthly gross salary from 2 788 euros.