Contract type : Public service fixed-term contract
Level of qualifications required : Graduate degree or equivalent
Fonction : PhD Position
This PhD is funded by the ES3CAP ("Embedded Smart Safe Secure Computing Autonomous Platform") collaborative project. The project aims to propose a software environment for multi-/many-core platforms, facilitating the transition from current architectures (distributed heterogenous or single-core/single-task) to industrially-viable centralized multi-/many-core solutions for high-performance, safe, and secure systems. The target market is that of new-generation critical systems (avionics, drones, autonomous vehicles).
In ES3CAP, Inria brings its expertise on parallel programming of critical software and on automatic allocation, real-time scheduling, and code generation for multi-/many-core platforms. Inria also brings its Lopht tool for automatic mapping and code generation, which has already been ported on the Kalray MPPA256 Bostan many-core. Lopht ensures by construction the functional correctness of the generated code and the respect of non-functional (real-time) requirements.
In previous work [1,2] we have developed an automatic parallelization
method and tool for multi-period hard real-time applications that
targets clusters of the Kalray MPPA256 Bostan many-core , chosen
for its excellent support for high-performance, timing predictable
execution. Our method produces parallel code that is functionally
correct and satisfies by construction non-functional (real-time)
requirements without compromising efficiency (speed, memory
footprint). To achieve this, our method relies on a tight integration
between timing analysis, real-time scheduling, and code generation
around a precise timing model of the execution platform.
Our approach has two key points:
- The timing model, built upon a model of the memory system of the
many-core allowing the precise and safe estimation of memory access
interferences between parallel threads.
- Real-time scheduling and code generation choices allowing
the synthesis of parallel code that is efficient and at the
same time allows scalable and precise timing analysis.
The objective of this PhD is to extend the existing memory model and
parallelization method to cover other shared memory multi-core
platforms, such as the new-generation Kalray MPPA Coolidge, Power
T1042, ARMv8 Cortex A53, or Infineon Aurix TC27x. Each of these
architectures poses different problems: heterogenous memory (mix of
SRAM, DDRAM, and FLASH with different access times), NUMA memory
(access times depend on the distance between core and RAM bank),
on-chip interconnect topology, etc. On traditional Power and ARM
multi-cores the architecture description is only partially known, so
timing guarantees can only be partial.
 K. Didier, D. Potop-Butucaru, G. Iooss, A. Cohen, J. Souyris,
P. Baufreton, A. Graillat. Efficient parallelization of
large-scale hard real-time applications. Inria Research Report
 T. Carle, D. Potop-Butucaru. Predicate-aware, makespan-preserving
software pipelining of scheduling tables. ACM TACO vol. 11(1),
State of the art.
Dissemination through paper writing and interaction with industrial and research partners.
We are looking for a candidate with an excellent record in computer science. Backgroud in the following fields is considered a plus: real-time systems, parallelization, distributed computing, compilation, programming languages, semantics, formal methods, computer architecture.
- Subsidized meals
- Partial reimbursement of public transport costs
- Leave: 7 weeks of annual leave + 10 extra days off due to RTT (statutory reduction in working hours) + possibility of exceptional leave (sick children, moving home, etc.)
- Possibility of teleworking (after 6 months of employment) and flexible organization of working hours
- Professional equipment available (videoconferencing, loan of computer equipment, etc.)
- Social, cultural and sports events and activities
- Access to vocational training
- Social security coverage
- Town/city : Paris
- Inria Center : CRI de Paris
- Starting date : 2019-05-01
- Duration of contract : 3 years
- Deadline to apply : 2019-07-31
- Inria Team : AT-PRO AE
PhD Supervisor :
Potop-butucaru Dumitru / firstname.lastname@example.org
Inria, the French national research institute for the digital sciences, promotes scientific excellence and technology transfer to maximise its impact. It employs 2,400 people. Its 200 agile project teams, generally with academic partners, involve more than 3,000 scientists in meeting the challenges of computer science and mathematics, often at the interface of other disciplines. Inria works with many companies and has assisted in the creation of over 160 startups. It strives to meet the challenges of the digital transformation of science, society and the economy.
Instruction to apply
Defence Security :
This position is likely to be situated in a restricted area (ZRR), as defined in Decree No. 2011-1425 relating to the protection of national scientific and technical potential (PPST).Authorisation to enter an area is granted by the director of the unit, following a favourable Ministerial decision, as defined in the decree of 3 July 2012 relating to the PPST. An unfavourable Ministerial decision in respect of a position situated in a ZRR would result in the cancellation of the appointment.
Recruitment Policy :
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