The Inria Bordeaux Sud-Ouest centre is one of Inria's nine centres and has around twenty research teams. The Inria centre is a major and recognized player in the field of digital sciences. It is at the heart of a rich R&D and innovation ecosystem: highly innovative SMEs, large industrial groups, competitiveness clusters, research and higher education players, laboratories of excellence, technological research institute...

The memory hierarchy of HPC platforms keeps becoming even more complex. Now that all processors have multiple levels of caches, memory itself is changing with the advent of different technologies with different performance characteristics. Heterogeneous memories first appeared in HPC several years ago with the Intel Xeon Phi processor. Custom strategies were implemented to place bandwidth-sensitive data buffers on the appropriate memory. The emergence on non-volatile memory DIMMs (that may be used either as fast storage or as slow but high-capacity memory) brought similar questions. Moreover several ARM and x86 platforms are going to combine HBM and DRAM on the road to exascale. There is a critical need for software stacks to learn portable ways to identify different kinds of memories, to abstract their characteristics in terms of performance, and to decide where to allocate which data buffer.

Heuristics for Heterogeneous Memory (H2M) is an ANR-DFG joint-project between the Inria TADaaM team in Bordeaux (France) and RWTH Aachen (Germany) to address these questions. The goal is to develop a hierarchy of programming abstractions to expose heterogeneous memory at different levels of detail and control, complemented by a set of required, vendor-neutral capabilities to
be provided by standards and intelligent runtime systems.

This postdoctoral position is funded by the H2M ANR-DFG project.

The role of the post-doctoral fellow will be:
* Identifying existing memory technologies and their characteristics, and quantifying the influence on application performance and design
* Designing low-level memory allocation strategies that could be used by runtimes and programming models for allocating on the appropriate memory target
* Developing methods and tools to identify the sensitivity of data buffers and compute kernels to memory bandwidth or latency
* Designing heuristics for selecting where to place tasks and data buffers depending on applications needs and hardware characteristics
* Defining high-level concepts and APIs for exposing allocation strategies to programming models and standards
* Evaluate the contributions with different applications on different hardware architectures

The postdoctoral fellow will develop these ideas in the software projects developed by the Inria TADaaM team. This notably includes the hwloc library for low-level hardware management and operating system interaction. Higher level ideas will be designed in collaboration with the RWTH Aachen team, with the goal of proposing ideas to the OpenMP standard committee. Modifications of the LLVM compile and runtimes might be used as a way to identify sensitivity and apply placement heuristics.

The candidate will be in charge of designing ideas and implement them in collaboration with other members of the project, as well as evaluating them with different applications on either real or simulated platforms. He will also be in charge of presenting the results during project meetings and in research papers.

The candidate should have a good knowledge of HPC architectures, including multicore processors and NUMA platforms, HPC software stack (low-level libraries, runtimes, parallel programming models), and some knowledge of operating systems and compilation techniques. Good C programming is required.

this will be a fixed-term contract

The gross monthly salary will be 2653 euros (before social charges on salary and monthly withholding taxes for income)