PhD Position F/M Reliable Deep Neural Network Hardware Accelerators

Context & background:

Deep Neural Networks (DNNs) [1] are currently one of the most intensively and widely used predictive models in the field of machine learning. DNNs have proven to give very good results for many complex tasks and applications, such as object recognition in images/videos, natural language processing, satellite image recognition, robotics, aerospace, smart healthcare, and autonomous driving. Nowadays, there is intense activity in designing custom Artificial Intelligence (AI) hardware accelerators to support the energy-hungry data movement, speed of computation, and memory resources that DNNs require to realize their full potential [2]. Furthermore, there is an incentive to migrate AI from the cloud into the edge devices, i.e., Internet-of-Things (IoTs) devices, in order to address data confidentiality issues and bandwidth limitations, given the ever-increasing internet-connected IoTs, and also to alleviate the communication latency, especially for real-time safety-critical decisions, e.g., in autonomous driving.

Hardware for AI (HW-AI), similar to traditional computing hardware, is subject to hardware faults (HW faults) that can have several sources: variations in fabrication process parameters, fabrication process defects, latent defects, i.e., defects undetectable at time-zero post-fabrication testing that manifest themselves later in the field of application, silicon ageing, e.g., time-dependent dielectric breakdown, or even environmental stress, such as heat, humidity, vibration, and Single Event Upsets (SEUs) stemming from ionization. All these HW faults can cause operational failures, potentially leading to important consequences, especially for safety-critical systems.

HW-AI comes with some inherent resilience to HW faults, similar to biological neural networks. Indeed, the statistical behavior of neural network architectures, as well as their high space redundancy and overprovisioning, naturally provide a certain tolerance to HW faults. HW-AI have the capability to circumvent to a large extent HW faults during the learning process. However, HW faults can still occur after training. Recent studies in the literature have shown that HW-AI is not always immune to such HW faults. Thus, inference can be significantly affected, leading to DNN prediction failures that are likely to lead to a detrimental effect on the application [3, 4, 5]. Therefore, ensuring the reliability of HW-AI platforms is crucial, especially when AI-HW is deployed in safety-critical and mission-critical applications, such as robotics, aerospace, smart healthcare, and autonomous driving.

Assessing the fault sensitivity of HW-AI systems is a highly complex, time-consuming, and energy-intensive process. The intricate nature of deep neural networks, with their vast parameter spaces and non-linear computations, makes it challenging to predict how faults will propagate and impact inference. Performing exhaustive fault injection campaigns to evaluate sensitivity requires extensive computational resources and long simulation runtimes, further exacerbating the time and energy costs. Additionally, real-world testing on AI hardware is even more demanding, as it involves running extensive workloads under varying fault conditions to capture all potential failure scenarios. This complexity is further amplified by the diverse architectures and hardware implementations of AI accelerators, each with unique fault behaviors. As a result, ensuring the reliability of HW-AI platforms demands significant effort, making it a crucial yet resource-intensive challenge, particularly for safety-critical applications.

Ph.D. thesis goal:

The goal of this thesis is twofold: (i) designing and developing an optimized algorithm-level fault injection framework to assess the resiliency of DNN HW accelerators to HW faults, to enable the application of low-cost selective fault-tolerance strategies; (ii) designing selective fault-tolerance approaches for DNN HW accelerators by using the analysis provided by the fault injection method.

The reliability improvements obtained with the above-described methodology will be measured, and a design space exploration will be carried out to obtain different DNN HW accelerator implementations that will provide different trade-offs between fault tolerance and energy efficiency.

More in detail, the Ph.D. student will design and develop a methodology to perform large-scale fault analysis on state-of-the-art DNN hardware architectures. The fault analysis will determine the set of malignant HW faults that mostly impact classification accuracy (or other DNN objectives, such as image segmentation) during the inference phase.

In particular, the student will (i) design a novel framework that enables accurate fault sensitivity evaluation having the same accuracy of gate level while maintaining computational efficiency; (ii) ensure that the framework effectively captures the intricate fault propagation characteristics of deep neural networks (DNNs) implemented in hardware.

Innovative methodologies will be explored to accelerate fault injection campaigns, such as hybrid analytical-empirical approaches and smart fault pruning techniques to minimize the number of required fault injections while maintaining high accuracy. Also, smart energy-efficient parallelization and distributed computing strategies to accelerate large-scale fault evaluation will be explored.

The proposed approach will be compared against state-of-the-art methodologies to validate improvements in speed and accuracy.

The developed framework will pave the way to innovative selective error correction mechanisms. A design space exploration will help to find the best solutions in terms of the trade-off between the fault tolerance level provided by protection mechanisms and the hardware overhead entailed in deploying these solutions.

The project will be part of a larger effort to design an end-to-end workflow that integrates seamlessly into the design and verification process of HW-AI platforms used in mission-critical applications.

Required technical skills:

• Good knowledge of computer architectures and embedded systems
• HW design: VHDL/Verilog basics, HW synthesis flow
• Programming knowledge (C/C++, python)
• Basics of Machine Learning (pytorch/tensorflow)
• Experience in fault-tolerant architectures is a plus

Candidates must have a Master’s degree (or equivalent) in Computer Engineering, or Electrical Engineering.